View CY7C343B-25HCHI_4207118.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

USE ULTRA37000TM FOR ALL NEW DESIGNS
CY7C343B
64-Macrocell MAX(R) EPLD
Features
* 64 MAX macrocells in 4 LABs * 8 dedicated inputs, 24 bidirectional I/O pins * Programmable interconnect array * Advanced 0.65-micron CMOS technology to increase performance * Available in 44-pin HLCC, PLCC * Lowest power MAX device
Functional Description
The CY7C343B is a high-performance, high-density erasable programmable logic device, available in 44-pin PLCC and HLCC packages. The CY7C343B contains 64 highly flexible macrocells and 128 expander product terms. These resources are divided into four Logic Array Blocks (LABs) connected through the Programmable Inter-connect Array (PIA). There are 8 input pins, one that doubles as a clock pin when needed. The CY7C343B also has 28 I/O pins, each connected to a macrocell (6 for LABs A and C, and 8 for LABs B and D). The remaining 36 macrocells are used for embedded logic. The CY7C343B is excellent for a wide range of both synchronous and asynchronous applications.
Logic Block Diagram
9 INPUT 11 INPUT 12 INPUT 13 INPUT DEDICATED INPUTS SYSTEM CLOCK LAB A 2 4 5 6 7 8 MACROCELL 1 MACROCELL 2 MACROCELL 3 MACROCELL 4 MACROCELL 5 MACROCELL 6 MACROCELLS 7 - 16 LAB D MACROCELL 56 MACROCELL 55 MACROCELL 54 MACROCELL 53 MACROCELL 52 MACROCELL 51 MACROCELL 50 MACROCELL 49 1 44 42 41 40 39 38 37 INPUT 35 INPUT/CLK 34 INPUT 33 INPUT 31
I/O PINS
I/O PINS
LAB B 15 16 17 18 19 20 22 23 MACROCELL 17 MACROCELL 18 MACROCELL 19 MACROCELL 20 MACROCELL 21 MACROCELL 22 MACROCELL 23 MACROCELL 24 MACROCELLS 25 - 32 (3, 14, 25, 36) (10, 21, 32, 43)
P I A
MACROCELLS57 - 64 LAB C MACROCELL 38 MACROCELL 37 MACROCELL 36 MACROCELL 35 MACROCELL 34 MACROCELL 33
I/O PINS
30 29 28 27 26 24
I/O PINS
MACROCELLS39 - 48
VCC GND
Cypress Semiconductor Corporation Document #: 38-03038 Rev. *B
*
3901 North First Street
*
San Jose, CA 95134
* 408-943-2600 Revised April 9, 2004
USE ULTRA37000TM FOR ALL NEW DESIGNS
Pin Configuration
HLCC, PLCC Top View
GND V CC I/O I/O I/O I/O I/O I/O I/O I/O I/O
CY7C343B
6 I/O I/O INPUT GND INPUT INPUT INPUT VCC I/O I/O I/O 7 8 9 10 11 12 13 14 15 16 17
5
4
3
2
1
44 43 42 41 40 39 38 37 36 35 34 33 32 I/O I/O I/O VCC INPUT INPUT/CLK INPUT GND INPUT I/O I/O
7C343
31 30 29
18 19 20 21 22 23 24 25 26 27 28 GND I/O I/O I/O I/O I/O I/O I/O I/O V CC I/O
Selection Guide
7C343B-25 Maximum Access Time (ns) 25 7C343B-30 30 7C343B-35 35
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ..................................-65C to+135C Ambient Temperature with Power Applied..............................................-65C to+135C Maximum Junction Temperature (Under Bias)................................................................. 150C Supply Voltage to Ground Potential[1] ............. -2.0V to+7.0V
DC Output Current, per Pin[1] ...................-25 mA to +25 mA DC Input Voltage[1] .........................................-2.0V to +7.0V
Operating Range[2]
Range Commercial Industrial Military Ambient Temperature 0C to +70C -40C to +85C -55C to +125C (Case) VCC 5V 5% 5V 10% 5V 10%
Note: 1. Minimum DC input is -0.3V. During transactions, the inputs may undershoot to -2.0V or overshoot to 7.0V for input currents less then 100 mA and periods shorter than 20 ns. 2. The Voltage on any input or I/O pin cannot exceed the power pin during power-up.
Document #: 38-03038 Rev. *B
Page 2 of 11
USE ULTRA37000TM FOR ALL NEW DESIGNS
Electrical Characteristics Over the Operating Range
Parameter VCC VOH VOL VIH VIL IIX IOZ tR tF Description Supply Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Level Input LOW Level Input Current Output Leakage Current Recommended Input Rise Time Recommended Input Fall Time VI = VCC or ground VO = VCC or ground Test Conditions Maximum VCC rise time is 10 ms IOH = -4.0 mA DC IOL = 8 mA DC
[3] [3]
CY7C343B
Min. 4.75(4.5) 2.4
Max. 5.25(5.5) 0.45
Unit V V V V V A A ns ns
2.0 -0.3 -10 -40
VCC+0.3 0.8 +10 +40 100 100
Capacitance
Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions VIN = 0V, f = 1.0 MHz VOUT = 0V, f = 1.0 MHz Max. 10 20 Unit pF pF
Note: 3. The IOH parameter refers to high-level TTL output current; the IOL parameter refers to low-level TTL output current.
AC Test Loads and Waveforms
R1 464 5V OUTPUT 50 pF INCLUDING JIG AND SCOPE R2 250 5V OUTPUT 5 pF INCLUDING JIG AND SCOPE R2 250 3.0V 10% GND <6 ns R1 464 ALL INPUT PULSES 90% 90% 10% <6 ns
(a)
(b)
Equivalent to: OUTPUT
THEVENIN EQUIVALENT (commercial/military) 163 1.75V
Document #: 38-03038 Rev. *B
Page 3 of 11
USE ULTRA37000TM FOR ALL NEW DESIGNS
Programmable Interconnect Array
The Programmable Interconnect Array (PIA) solves interconnect limitations by routing only the signals needed by each logic array block. The inputs to the PIA are the outputs of every macrocell within the device and the I/O pin feedback of every pin on the device. Unlike masked or programmable gate arrays, which induce variable delay dependent on routing, the PIA has a fixed delay. This eliminates undesired skews among logic signals, which may cause glitches in internal or external logic. The fixed delay, regardless of programmable interconnect array configuration, simplifies design by ensuring that internal signal skews or races are avoided. The result is simpler design implementation, often in a single pass, without the multiple internal logic placement and routing iterations required for a programmable gate array to achieve design timing objectives.
CY7C343B
Typical ICC vs. fMAX
200
ICC ACTIVE (mA) Typ.
150
VCC = 5.0V Room Temp.
100
50
Design Recommendations
Operation of the devices described herein with conditions above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. Exposure to absolute maximum ratings conditions for extended periods of time may affect device reliability. The CY7C343B contains circuitry to protect device pins from high static voltages or electric fields; however, normal precautions should be taken to avoid applying any voltage higher than maximum rated voltages. For proper operation, input and output pins must be constrained to the range GND < (VIN or VOUT) < VCC. Unused inputs must always be tied to an appropriate logic level (either VCC or GND). Each set of VCC and GND pins must be connected together directly at the device. Power supply decoupling capacitors of at least 0.2 F must be connected between VCC and GND. For the most effective decoupling, each VCC pin should be separately decoupled to GND, directly at the device. Decoupling capacitors should have good frequency response, such as monolithic ceramic types.
0 100 Hz
1 kHz
10 kHz
100 kHz
1 MHz 10 MHz
50 MHz
MAXIMUM FREQUENCY
Output Drive Current
IO OUTPUT CURRENT (mA) TYPICAL
250 IOL 200 150 100 IOH 50 VCC = 5.0V Room Temp.
0
1
2
3
4
5
Timing Considerations
Unless otherwise stated, propagation delays do not include expanders. When using expanders, add the maximum expander delay tEXP to the overall delay. Similarly, there is an additional tPIA delay for an input from an I/O pin when compared to a signal from a straight input pin. When calculating synchronous frequencies, use tS1 if all inputs are on the input pins. When expander logic is used in the data path, add the appropriate maximum expander delay, tEXP to tS1. Determine which of 1/(tWH + tWL), 1/tCO1, or 1/(tEXP + tS1) is the lowest frequency. The lowest of these frequencies is the maximum data path frequency for the synchronous configuration.
VO OUTPUT VOLTAGE (V)
When calculating external asynchronous frequencies, use tAS1 if all inputs are on dedicated input pins. When expander logic is used in the data path, add the appropriate maximum expander delay, tEXP to tAS1. Determine which of 1/(tAWH + tAWL), 1/tACO1, or 1/(tEXP + tAS1) is the lowest frequency. The lowest of these frequencies is the maximum data path frequency for the asynchronous configuration. The parameter tOH indicates the system compatibility of this device when driving other synchronous logic with positive input hold times, which is controlled by the same synchronous clock. If tOH is greater than the minimum required input hold time of the subsequent synchronous logic, then the devices are guaranteed to function properly with a common synchronous clock under worst-case environmental and supply voltage conditions.
Document #: 38-03038 Rev. *B
Page 4 of 11
USE ULTRA37000TM FOR ALL NEW DESIGNS
EXPANDER DELAY tEXP
CY7C343B
REGISTER OUTPUT DELAY tOD tXZ tZX
INPUT INPUT DELAY tIN
LOGIC ARRAY CONTROL DELAY tLAC LOGIC ARRAY DELAY tLAD
tCLR tPRE tRSU tRH tRD
INPUT/ OUTPUT
tCOMB tLATCH
SYSTEM CLOCK DELAY tICS PIA DELAY tPIA CLOCK DELAY tIC
FEEDBACK DELAY tFD
I/O DELAY tIO
Figure 1. CY7C343B Internal Timing Model
External Synchronous Switching Characteristics Over Operating Range
7C343B-25 Parameter tPD1 tPD2 tSU tCO1 tH tWH tWL fMAX tCNT tODH fCNT Description Dedicated Input to Combinatorial Output Delay[4] I/O Input to Combinatorial Output Delay[4] Global clock setup time Input Hold Time from Synchronous Clock Input Synchronous Clock Input HIGH Time Synchronous Clock Input LOW Time Maximum Register Toggle Frequency[5] Minimum Global Clock Period Output Data Hold Time After Clock Maximum Internal Global Clock Frequency[6] Com'l/Ind Com'l/Ind Com'l/ Ind Com'l/Ind Com'l/Ind Com'l/Ind Com'l/Ind Com'l/Ind Com'l/Ind Com'l/Ind 2 50 15 14 0 8 8 62.5 20 2 40 0 10 10 50 25 2 33.3 Min. Max. 25 40 20 16 0 12.5 12.5 40 30 7C343B-30 Min. Max. 30 45 25 20 7C343B-35 Min. Max. 35 55 Unit ns ns ns ns ns ns ns MHz ns ns MHz
Synchronous Clock Input to Output Delay[3] Com'l/Ind
Notes: 4. C1 = 35 pF. 5. The fMAX values represent the highest frequency for pipeline data. 6. This parameter is measured with a 16-bit counter programmed into each LAB.
Document #: 38-03038 Rev. *B
Page 5 of 11
USE ULTRA37000TM FOR ALL NEW DESIGNS
External Asynchronous Switching Characteristics Over Operating Range
7C343B-25 Parameter tACO1 tAS1 tAH tAWH tAWL tACNT fACNT Description Asynchronous Clock Input to Output Delay[4] Com'l/Ind Dedicated Input or Feedback Set-Up Time to Com'l/Ind Asynchronous Clock Input Input Hold Time from Asynchronous Clock Input Asynchronous Clock Input HIGH Time[7] Asynchronous Clock Input LOW Time[7] Minimum Internal Array Clock Frequency Com'l/Ind Com'l/Ind Com'l/Ind Com'l/Ind 50 5 6 11 9 20 40 Min. Max. 25 6 8 14 11 25 7C343B-30 Min. Max. 30
CY7C343B
7C343B-35 Min. 8 10 16 14 30 33.3 Max. 35 Unit ns ns ns ns ns ns MHz
Maximum Internal Array Clock Frequency[6] Com'l/Ind
Internal Switching Characteristics Over Operating Range
7C343B-25 Parameter tIN tIO tEXP tLAD tLAC tOD tZX tXZ tRSU tRH tLATCH tRD tCOMB tIC tICS tFD tPRE tCLR tPIA Description Dedicated Input Pad and Buffer Delay Com'l/Ind I/O Input Pad and Buffer Delay Expander Array Delay Logic Array Data Delay Logic Array Control Delay Output Buffer and Pad Delay[4] Output Buffer Enable Delay[4] Output Buffer Disable Delay[8] Register Set-Up Time Relative to Clock Signal at Register Register Hold Time Relative to Clock Signal at Register Flow-Through Latch Delay Register Delay Transparent Mode Delay Asynchronous Clock Logic Delay Synchronous Clock Delay Feedback Delay Asynchronous Register Preset Time Asynchronous Register Clear Time Programmable Interconnect Array Delay Time Com'l/Ind Com'l/Ind Com'l/Ind Com'l/Ind Com'l/Ind Com'l/Ind Com'l/Ind Com'l/Ind Com'l/Ind Com'l/Ind Com'l/Ind Com'l/Ind Com'l/Ind Com'l/Ind Com'l/Ind Com'l/Ind Com'l/Ind Com'l/Ind 6 4 3 1 3 14 3 1 5 5 14 Min. Max. 5 6 12 12 10 5 10 10 8 6 4 2 4 16 2 1 6 6 16 7C343B-30 Min. Max. 7 6 14 14 12 5 11 11 12 8 4 2 4 18 1 2 7 7 20 7C343B-35 Min. Max. 11 11 20 14 13 6 13 13 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Notes: 7. This parameter is measured with a positive-edge-triggered clock at the register. For negative-edge clocking, the tACH and tACL parameter must be swapped. 8. C1 = 5 pF.
Document #: 38-03038 Rev. *B
Page 6 of 11
USE ULTRA37000TM FOR ALL NEW DESIGNS
Switching Waveforms
Internal Synchronous
CLOCK FROM LOGIC ARRAY DATA FROM LOGIC ARRAY tXZ OUTPUT PIN tZX HIGH IMPEDANCE STATE tRD tOD
CY7C343B
Internal Asynchronous
tIOR t CLOCK PIN tIN CLOCK INTO LOGIC ARRAY CLOCK FROM LOGIC ARRAY DATA FROM LOGIC ARRAY tRD,tLATCH REGISTER OUTPUT TO LOCAL LAB LOGIC ARRAY tPIA REGISTER OUTPUT TO ANOTHER LAB tFD tCLR,tPRE tFD tAWH tAWL tF
tIC
tSU
tRH
Internal Synchronous
SYSTEM CLOCK PIN tIN SYSTEM CLOCK AT REGISTER DATA FROM LOGIC ARRAY tICS
tRSU
tRH
Document #: 38-03038 Rev. *B
Page 7 of 11
USE ULTRA37000TM FOR ALL NEW DESIGNS
Switching Waveforms (continued)
Internal Combinatorial
tIN INPUT PIN t IO I/O PIN tEXP EXPANDER ARRAY DELAY tLAC, tLAD LOGIC ARRAY INPUT
CY7C343B
LOGIC ARRAY OUTPUT
tCOMB
OUTPUT PIN
tOD
External Combinatorial
DEDICATED INPUT/ I/O INPUT tPD1/tPD2 COMBINATORIAL OUTPUT
External Synchronous tWH tWL
SYNCHRONOUS CLOCK PIN SYNCHRONOUS CLOCK AT REGISTER DATA FROM LOGIC ARRAY
tSU
tH
tCO1
REGISTERED OUTPUTS
External Asynchronous
DEDICATED INPUTS OR REGISTERED FEEDBACK tAS1 ASYNCHRONOUS CLOCK INPUT tAH tAWH tAWL
Document #: 38-03038 Rev. *B
Page 8 of 11
USE ULTRA37000TM FOR ALL NEW DESIGNS
Ordering Information
Speed (ns) 25 30 35 Ordering Code CY7C343B-25HC/HI CY7C343B-25JC/JI CY7C343B-30JC/JI CY7C343B-35HC/HI CY7C343B-35JC/JI Package Name H67 J67 J67 H67 J67 Package Type 44-Pin Windowed Leaded Chip Carrier 44-Lead Plastic Leaded Chip Carrier 44-Lead Plastic Leaded Chip Carrier 44-Pin Windowed Leaded Chip Carrier 44-Lead Plastic Leaded Chip Carrier
CY7C343B
Operating Range Commercial/Industrial Commercial/Industrial Commercial/Industrial
Package Diagrams
44-Pin Windowed Leaded Chip Carrier H67
51-80079-**
Document #: 38-03038 Rev. *B
Page 9 of 11
USE ULTRA37000TM FOR ALL NEW DESIGNS
Package Diagrams (continued)
44-Lead Plastic Leaded Chip Carrier J67
CY7C343B
51-85003-*A
MAX is a registered trademark and Ultra37000 is a trademark of Cypress Semiconductor Corporation. All products and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-03038 Rev. *B
Page 10 of 11
(c) Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
USE ULTRA37000TM FOR ALL NEW DESIGNS
Document History Page
Document Title: CY7C343B 64-Macrocell Max (R) EPLD Document Number: 38-03038 REV. ** *A *B ECN NO. 106461 122237 213375 Issue Date 07/11/01 12/28/02 See ECN Orig. of Change SZV RBI FSG Description of Change Change from Spec Number: 38-00862 to 38-03038
CY7C343B
Power up requirements added to Operating Range Information Added note to title page: "Use Ultra37000 For All New Designs"
Document #: 38-03038 Rev. *B
Page 11 of 11

▲Up To Search▲

Price & Availability of CY7C343B-25HCHI

	To Download CY7C343B-25HCHI Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .